Sequential Logic Circuits MCQs

Digital Electronics MCQs

1. For which of following flip-flops, the output is clearly defined for all combinations of to inputs?

a. D flip-flop

b. J-K flip-flop

c. R-S flip-flop

d. None of these

2. What J-K input condition will always set Q+ upon the occurrence of the active clock transition?

a. J = 1, K = 0

b. J = 1, K = 1

c. J = 0, K = 1

d. J = 0, K = 0

3. In a J-K flip-flop, toggle means___.

a. Change the output to the opposite state

b. Set Q = 1 and Q(bar) = 0

c. Set Q = 0 and Q(bar) = 1

d. No change in the input

4. The output of S-R flip-flop when S = 1, R = 0 is______.

a. High impedance

b. No change

c. High

d. Low

5. Assertion(A): An unlocked flip-flop is called a latch.

Reason(R): A latch is constructed using two cross-coupled NAND gates or NOR gates.

a. A is false but R is true

b. A is true but R is false

c. Both A ad R are true but R is not the correct explanation of A

d. Both A and R are true but R is the correct explanation of A

6. Race around condition always arise in a______.

a. Digital circuit

b. Synchronous circuit

c. Asynchronous circuit

d. Combinational circuit

7. A T-flip-flop can be made from a J-K flip-flop by using______.

a. An OR gate

b. A AND gate

c. An XOR gate

d, None of these

8. The J-K master-slave flip-flop is different from the S-R flip-flop (Both made with NAND gates)

in that, it has_____.

a. A much shorter delay

b. A valid output when both inputs are 1

c. No need of a clock

d. No race around condition

9. In a clocked S_R flip-flop made with NAND gates, the input combination S = 1, R = 1, is not permitted because it leads to_____.

a. The output becoming available before the clock goes low

b. An unpredictable output when the inputs become zero

c. Both the outputs being zero simultaneously

d. A race around condition