MCQs on Counters

Digital Electronics MCQs

1. How many flip-flops are required for Mod-16 counter?

a. 5

b. 3

c. 6

d. 4

2. A ring counter consisting of five flip-flops will have______.

a. 10 states

b. 5 states

c. infinite states

d. 32 states

3. If the input to T-flip flop is 100 Hz signal, the final output of the three T-flip flops in cascade is______.

a. 12.5 Hz

b. 500 Hz

c. 1000 Hz

d. 333 Hz

4. A 4-bit synchronous counter uses flip-flops with propagation delay times of 20 ms each. The maximum possible time required for change of state will be____.

a. 10 ns

b. 30 ns

c. 20 ns

d. 60 ns

5. How many flip-flops are required to construct a decade counter?

a. 4

b. 2

c. 10 

d. 3

6. If the clock input applied to a cascaded Mod-6 and Mod-4 counter is 48kHz, the output of the cascaded arrangement would be_____.

a. 12 kHz

b. 8 kHz

c. 4.8 kHz

d. 2 kHz

7. For what minimum value of propagation delay in each FF will a 10-bit ripple counter skip a count when it is clocked at 10 MHz?

a. 100ns

b. 5 ns

c. 10 ns

d. None of these

8. A binary ripple counter is required to count up to 16,383₁₀ . If the clock frequency is 8192MHz, what is the frequency at the output of the MSB?

a. 500 kHz

b. 150 kHz

c. 225 kHz

d. 625 kHz

9. A 25 : 1 ripple counter is required. If 4 flip-flops are available on a chip, how many chips are needed?

a. 3 

b. 1

c. 2

d. 25

10.  Minimum number of J-K flip-flops needed to construct a BCD counter is______.

a. 5

b. 4

c. 3

d. 2

11. The decoding error of the counter can be avoided by______.

a. Increasing propagation delay of flip-flops used in the counter

b. Using very fast logic

c. Using the strobe signal

d. Reducing the propagation delay of flip-flops used in the counter

12. A switch tailoring counter is made by using a single D-flip-flop. The resulting circuit is a______.

a. SR flip-flop

b. JK flip-flop

c. D flip-flop

d. T flip-flop