MCQs on Microprocessor and Microcontrollers Part-5

Microprocessor and Microcontrollers

1. The upper 128 bytes of an internal data memory from 80H through FFH usually represent _______.

a. general-purpose registers

b. special function registers

c. stack pointers

d. program counters

2. What is the bit addressing range of addressable individual bits over the on-chip RAM?

a. 00H to FFH

b. 01H to 7FH

c. 00H to 7FH

d. 80H to FFH

3. What is the divisional range of program memory for internal and external memory portions respectively when enable access pin is held high (unity)?

a. 0000H – 0FFFH & 1000H – FFFFH

b. 0000H – 1000H & 0FFFH – FFFFH

c. 0001H – 0FFFH & 01FFH – FFFFH

d. None of the above

4. Consider the following statements. Which of them is/are correct in case of program execution related to program memory?

a. External Program memory execution takes place from 1000H through 0FFFFH only when the status of EA pin is high (1)

b. External Program memory execution takes place from 0000H through 0FFFH only when the status of EA pin is low (0)

c. Internal Program execution occurs from 0000H through 0FFFH only when the status of EA pin is held low (0)

d. Internal program memory execution occurs from 0000H through 0FFFH only when EA pin is held high (1)

a. A & C

b. B & D

c. A & B

d. Only A

5. How does the processor respond to an occurrence of the interrupt?

a. By Interrupt Service Subroutine

b. By Interrupt Status Subroutine

c. By Interrupt Structure Subroutine

d. By Interrupt System Subroutine

6. Which address/location in the program memory is supposed to get occupied when CPU jump and execute instantaneously during the occurrence of an interrupt?

a. Scalar

b. Vector

c. Register

d. All of the above

7. Which location specify the storage/loading of vector address during the interrupt generation?

a. Stack Pointer

b. Program Counter

c. Data Pointer

d. All of the above

8. Match the following :

a. ISS —————————– 1. Monitors the status of interrupt pin

b. IER —————————– 2. Allows the termination of ISS

c. RETI ————————— 3. MCS-51 Interrupts Initialization

d. INTO ————————– 4. Occurrence of high to low transition level

a. A-1, B-2, C-3, D-4

b. A-3, B-2, C-4, D-1

c. A-1, B-3, C-2, D-4

d. A-4, B-3, C-2, D-1

9. What kind of triggering configuration of external interrupt intimate the signal to stay low until the generation of subsequent interrupt?

a. Edge-Triggering

b. Level Triggering

c. Both a & b

d. None of the above

10. Which among the below mentioned reasons is/are responsible for the generation of Serial Port Interrupt?

a. Overflow of timer/counter 1

b. High to low transition on pin INT1

c. High to low transition on pin INT0

d. Setting of either TI or RI flag

a. A & B

b. Only B

c. C & D

d. Only D